The present invention relates to a charge pump circuit for generating, for example, write voltage or erase voltage or the like in nonvolatile semiconductor storage devices by boosting or lowering the power supply voltage.
For next-generation flash memories, there is a demand for further lower voltage, smaller power and lower cost (downsizing of circuits) than today's counterparts. In particular, charge pump circuits for generating a high voltage required to write or erase data into or from memory cells occupy a large portion of the chip area, and therefore it is important to implement the size reduction.
The charge pump circuit is a circuit for generating a voltage, or a negative voltage, higher than a power supply voltage by boosting or lowering the power supply voltage. A charge pump for generating a negative voltage to be used for block erasure in NOR flash memories (hereinafter, referred to as negative-voltage charge pump) generates a negative voltage of about -11 V from a power supply voltage (3 V or 5 V). However, with the circuit structure of conventional negative-voltage charge pumps, the circuit would necessarily be upsized acceleratively to obtain the same output from further lower power supply voltages with a view to the voltage reduction, which has been an obstacle to cost reduction.
Conventionally, as one of the circuit structure of the negative-voltage charge pump circuit, there has been a method in which a circuit part for fall of voltage is made up of P-channel transistors. Below given are a brief description of this negative-voltage charge pump using P-channel transistors as well as problems involved in the case where P-channel transistors are used.
An example of the negative-voltage charge pump circuit using P-channel transistors is shown in FIG. 11. In the figure, a portion surrounded by broken line is a pump cell 1 that serves as a basic unit of a charge pump, and a negative-voltage charge pump circuit is made up by connecting several pump cells 1 in series.
Clocks clk1-clk4 as shown in FIG. 12 are inputted to individual clock input terminals CLK1-CLK4 of the pump cells 1. More specifically, clocks clk1, clk2 are inputted to the clock input terminals CLK1, CLK2 of the first-stage pump cell 1, clocks clk3, clk4 are inputted to the clock input terminals CLK3, CLK4 of the second-stage pump cell 1, and clocks clk1, clk2 are inputted to the clock input terminals CLK1, CLK2 of the third-stage pump cell 1. Similarly for the following, clocks clk1, clk2 are inputted to the clock input terminals CLK1, CLK2 of pump cells 1 of odd-numbered stages. By contrast, clocks clk3, clk4 which are shifted 180 degrees with respect to the clocks clk1, clk2 are inputted to the clock input terminals CLK3, CLK4 of pump cells 1 of even-numbered stages.
Now the operation of the pump cell 1 is described by taking a stage 2 in FIG. 11 as an example. Voltage of a node OUT1, which is the input of the stage 2, oscillates at an amplitude of a power supply voltage Vcc generally in synchronization with the clock clk2 as shown by out1 in FIG. 13, by action of a capacitor C4 of the preceding stage 1 and the clock clk2 inputted to this capacitor C4. Meanwhile, voltage of a node OUT2, which is the output of the stage 2, oscillates at the amplitude of the power supply voltage Vcc generally in synchronization with the clock clk4 as shown by out2 in FIG. 13, by action of a capacitor C6 inside the stage 2 and the clock clk4 inputted to this capacitor C6.
Between the node OUT1 and the node OUT2, is provided a transistor M7 having a role of transferring charges between the two nodes OUT1 and OUT2. The voltage of a node B in FIG. 11, when the clock clk4 is an "L" with a transistor M6 conducting, makes a transition at the same voltage as the node OUT1 as shown by broken line B in FIG. 13. In contrast to this, when the clock clk4 is an "H" with the transistor M6 non-conducting, the voltage makes a transition generally in synchronization with the clock clk3 by action of a capacitor C5 connected to the node B and the clock clk3 inputted to this capacitor C5.
Therefore, in the state that the voltage of the node OUT1 has been pushed down by the capacitor C4 and that the voltage of the node OUT2 has been pushed up by the capacitor C6, the node B becomes a voltage lower than the source voltage of the transistor M7 so that the transistor M7 is opened, allowing the charges to be delivered. Then, in any other state, the transistor M7 is closed. Therefore, by making up a negative-voltage charge pump by connecting in series the pump cells 1 having the above construction, a negative voltage Vneg can be taken out.
However, the conventional negative-voltage charge pump circuit has the following problems. That is, the negative-voltage charge pump circuit has a capability of lowering the input voltage by an extent of (Vcc-.alpha.) (where .alpha.&gt;0) per pump cell 1 of one stage. However, the value of .alpha. varies from one pump cell 1 to another due to the voltage inside the pump cell 1. The reason of this is that transfer-use transistors M5, M7, M9 are affected by the backgating effect. For a transistor, the larger the voltage difference between its source and well is, the larger the threshold voltage of the transistor becomes due to the backgating effect. In this case, the P-channel transistors constituting the transfer-use transistors M5, M7, M9 cannot be made be have their n-well portion voltage lower than the substrate voltage (0 V). Meanwhile, the later stage the pump cells 1 belongs to, the lower the source voltage of the transistors M5, M7, M9 becomes. Accordingly, the later the stage in the charge pump is, the larger the voltage difference between source and well becomes so that the influence of the backgating effect increases. That is, if .alpha. value of the "i"th-stage pump cell 1.sub.i is .alpha..sub.i (i=1, 2, . . . , n), then EQU 0.ltoreq..alpha..sub.i.ltoreq..alpha..sub.2.ltoreq. . . . .ltoreq..alpha..sub.n.
Because voltage reduction of the output voltage per pump cell 1 of one stage becomes smaller in later stages of the charge pump, the number of stages of pump cells 1 needs to be increased proportional to the extent of the voltage reduction. Also, the more the power supply voltage lowers, the more the number of stages of pump cells 1 needs to be increased. Unfortunately, however, increasing the number of stages of pump cells 1 would cause the voltage loss due to the backgating effect to increase proportionally as described above, which in turn gives rise to a need for further increasing the number of stages of pump cells 1 in order to make up for the increased voltage loss. Thus, as a result of voltage reduction of the power supply voltage Vcc, the chip area occupied by the charge pump circuit is increased acceleratively.
Also, when the power supply voltage Vcc is lowered as described above, it can occur that at the "i"th-stage pump cell 1.sub.i, EQU Vcc-.alpha..sub.i &lt;0.
In this case, no matter how many additional pump cells 1 are connected, the voltage of the output voltage Vneg comes not to lower any more. For example, when Vcc=1.8 V, no matter how many additional pump cells 1 are connected, the output Vneg of the negative-voltage charge pump could be no more than -8 V. Therefore, some devise is needed to generate a high voltage or a negative voltage of large absolute value with a low power supply voltage.
As a solution to the above issue that increasing the number of stages of pump cells would cause the voltage loss due to the backgating effect to increase proportionally, there is a method that the amplitude of the clock clk inputted to the pump cell 1 is made larger than the power supply voltage Vcc by some means, thereby reducing the loss due to the backgating effect.
For example, Japanese Patent Laid-Open Publication HEI 6-208798 has proposed a method for enlarging the clock amplitude of a main pump by means of an auxiliary pump. That is, as shown in FIG. 14, an intermediate voltage higher than a power supply voltage Vcc and lower than an output Vpp is generated by the auxiliary pump 5, and this intermediate voltage is used as power supply for a clock driver 6. Thus, a clock signal larger in amplitude than the power supply voltage Vcc is obtained. Then, by using the clock signal larger in amplitude than the power supply voltage Vcc as a clock signal for the main pump 7, there can be obtained an effect of reducing the number of the stages of pump cells in the main pump 7 and an effect of relatively reducing the voltage loss due to the backgating effect per one-stage pump cell. In this way, the issue of increasing effect of the backgating effect caused by the power supply voltage Vcc being low is avoided.
Further, because an increase in the threshold voltage of the transfer-use transistors M5, M7, M9 matters for the negative-voltage charge pump shown in FIG. 11, there is a method that a bootstrap circuit is added only to clocks of the transfer-use transistors. FIG. 15 shows a negative-voltage charge pump circuit in which bootstrap circuits 11, 12 are connected to the clock input terminals CLK1, CLK2 in the negative-voltage charge pump shown in FIG. 11.
This negative-voltage charge pump shown in FIG. 15A operates as follows. As shown in FIG. 15B, when an input clkin of the bootstrap circuit 12 is at a logical level "L", a transistor 13 conducts so that an output clkout goes 0 V. At the same time, a node 14 is charged up to a voltage of (Vcc-Vthn) (where Vthn: threshold voltage) via a transistor 15. Next, when the logical level of the input clkin goes "H", the transistor 13 goes non-conductive while the node 14 is boosted higher than the power supply voltage Vcc. For example, assuming that the total of the load capacities connected to the node 14 is Cload (Cload=C.sub.18 + . . . +C.sub.20) and that the capacitance of a capacitor C15 is C.sub.15, then the voltage of the node 14 is boosted, according to a capacity ratio between capacitance C.sub.15 and capacitance Cload in the bootstrap circuit 12, ideally to EQU Vcc-Vthn+Vcc.multidot.C.sub.15 /(C.sub.15 +Cload) (1).
This boosted voltage of the node 14 is outputted as a clkout through a transistor 18.
By these operations, when the clock clkin is inputted to the bootstrap circuits 11, 12, a clock made larger in amplitude than Vcc can be taken out. Then, by using this clock clkout, which is larger in amplitude than Vcc as the clock clk given to the transfer-use transistor, influence of the backgating effect can be alleviated proportionally to the amplitude increase of the clock clk. In addition, according to the foregoing Equation (1), the larger the capacitance C.sub.15 in the bootstrap circuits 11, 12 is made, the greater the amplitude of the clock clkout outputted by the bootstrap circuits 11, 12 becomes, so that the effect of reducing the influence of the backgating effect also becomes greater.
In the two examples described above, the reduction in pump efficiency due to increase in the threshold voltage of the transistors caused by the backgating effect has been resolved. However, in either case, there is a need for adding new circuits for the auxiliary pump 5, the bootstrap circuits 11, 12 and the like. This causes an increase in the circuit area, and moreover an increase in cost, disadvantageously. Both the auxiliary pump 5 and the bootstrap circuits 11, 12 require a capacitor for voltage boost, and this capacitor would produce less effects unless larger in capacity (i.e., larger in area) than the capacitor inside the main pump. Accordingly, the above-described two examples would result in a significant cost increase. Furthermore, in the above two examples, although the influence of the backgating effect can be alleviated, the backgating effect is not eliminated.
As a method for preventing the occurrence of the backgating effect, there is a method that N-channel transistors of the triple-well system are used for the negative-voltage charge pump. FIG. 16 shows a circuit diagram of a negative-voltage charge pump using N-channel transistors of the triple-well system. Now the basic operation of this negative-voltage charge pump is explained according to FIG. 16.
As in the case of a negative-voltage charge pump using P-channel transistors shown in FIG. 11, clocks clk1-clk4 as shown in FIG. 17 are inputted to pump cells 21 surrounded by broken line. Voltage of a node OUT1, which is an input of the stage 2, oscillates at a voltage difference of power supply voltage Vcc generally in synchronization with the clock clk2 as shown by out1 in FIG. 18, by an action of a capacitor C10 of the preceding-stage pump cell 21 and the clock clk2 inputted to this capacitor C10. Meanwhile, voltage of a node OUT2, which is an output of the stage 2, oscillates at a voltage difference of the power supply voltage Vcc generally in synchronization with the clock clk4 as shown by out2 in FIG. 18, by an action of a capacitor C12 and the clock clk4 inputted to this capacitor C12. The voltage of a node C in FIG. 16, when the input signal out1 is at an "H" level with the transistor M12 conducting, makes transition at the same voltage as the node OUT2 as shown by broken line C in FIG. 18. In contrast to this, when the input signal out1 is at an "L" level with the transistor M12 non-conducting, the voltage makes transition generally like the clock clk3 by an action of a capacitor C11 connected to the node C and the clock clk3 inputted to this capacitor C11.
Therefore, in the state that the voltage of the node OUT2 is pushed up by the capacitor C11 and that the voltage of the node OUT1 is pushed down by the capacitor C10, the node C becomes higher in voltage than the source voltage of the transistor M13 so that the transfer-use transistor M13 is opened, allowing the charges to be transferred.
In this negative-voltage charge pump circuit, the p-well voltage for individual transistors is derived from the source. Therefore, the voltage difference between well and source is approximately 0 V so that the backgating effect can be neglected. As a consequence, there occurs no decrease in pump efficiency due to the backgating effect.
However, in this negative-voltage charge pump circuit, in which the p-well voltage of each transistor is simply taken from the source of the same transistor, if a period in which EQU V.sub.source =V.sub.pwell &gt;V.sub.drain +V.sub.bi
(where V.sub.bi is a voltage barrier between p-well and source) is present in each transistor within the pump cell 21, then the thyristor structure parasitic within the N-channel transistor goes active, causing a latch-up or charge leak. For example, at a time point t.sub.B in FIG. 18, EQU voltage of out1&lt;voltage of out2,
and, for the transistor M13 in FIG. 16, EQU V.sub.source =V.sub.pwell &gt;V.sub.drain.
Then, while the charge pump circuit is in the steady state, there is a voltage difference of about Vcc on average between the voltage of out1 and the voltage of out2, and both signals out1, out2 are oscillating at a voltage difference of Vcc, respectively. As a result, the value of (V.sub.source -V.sub.drain) at the time point t.sub.B is small, thus making latch-up or charge leak less likely to occur.
At a start-up of the pump, however, because all the nodes are of the same voltage, the value of (V.sub.source -V.sub.drain) is large, making it likely to occur that V.sub.source -V.sub.drain &gt;V.sub.bi at the timing of the time point t.sub.B. Accordingly, this negative-voltage charge pump circuit has a large possibility that latch-up or charge leak is caused at a pump start-up, and hence the circuit can be said to be a risky circuit.
As a countermeasure for preventing the occurrence of latch-up or charge leak in the negative-voltage charge pump using N-channel transistors, it is recommendable to ensure that the p-well voltage of each transistor is lower than the drain voltage and the source voltage. One concrete example of this is a negative-voltage charge pump circuit having a constitution shown in FIG. 19.
In the negative-voltage charge pump circuit shown in FIG. 19, pump cells 22 each having a circuit structure shown in FIG. 20 are connected in series so as to make up a main pump 23. Each pump cell 22 is provided with an input terminal WELL for inputting the p-well voltage as shown in FIG. 20, and an output terminal of an auxiliary pump 24 other than the main pump 23 is connected to this input terminal WELL. Then, before driving the main pump 23, the p-well voltage of the N-channel transistor in each of the pump cells 22 constituting the main pump 23 is lowered by the auxiliary pump 24 beforehand. In this way, by ensuring that the p-well voltage is necessarily lower than the drain voltage and the source voltage at a pump start-up, the possibility of latch-up or charge leak is avoided.
It is noted that the auxiliary pump 24 is designed to charge the p-well of each of the pump cells 22 constituting the main pump 23, and therefore does not need to have a current supplying ability. However, in order to securely lower the p-well voltage of the main pump 23, the voltage dropping ability of the auxiliary pump 24 that input the p-well voltage to the succeeding-stage pump cell 22 in the main pump 23 must be higher than the voltage dropping ability of the corresponding pump cell 22 of the main pump 23. For this reason, this negative-voltage charge pump circuit involves safe but relatively large-scaled additional circuits (auxiliary pumps 24), causing the circuit area to increase and inevitably involving a cost increase.
As described above, such a conventional negative-voltage charge pump circuit as shown in FIG. 11 has a problem that making the power supply voltage lower causes the loss due to the backgating effect to relatively increase so that the charge pump efficiency lowers. Although various types of negative-voltage charge pump circuits as described above have been available to avoid this problem, none of those circuits cannot afford to resolve the two issues of "cost increase" and "risks of latch-up and charge leak".